Direct Memory Access (DMA)
The transfer of data between a fast storage device such as magnetic disk and memory is often limited by the speed of CPU. Removing the CPU from the path and letting the peripheral device manage the memory buses directly would improve the speed of transfer. This transfer technique is called Direct Memory Access.
Here CPU does not have any control of the memory buses. A DMA controller takes over the buses to manage the transfer directly betwen the I/O device and memory.
CPU bus signal for DMA transfer
DMA transfer has two control signals BR (Bus Request) and BG (Bus Grant) to facilitate the transfer.
It is the input used by the DMA controller to request the CPU to relinquish control of buses. When this input is active the CPU terminates the execution of current instructions and places the address bus, data and read & write lines into a high-impedence state; which means the output is disconnected and does not logic significance.
The CPU activates the bus grant (BG) output to inform the DMA that the buses are in high-impendence state. Therefore DMA can now take control of buses to conuct memory transfers without processor interventation. When the DMA terminates the transfer it disables the bus request (BR) line, then the CPU disables the bus grant (BG), takes control of the buses and returns to its normal operation.
DMA communicates directly with the memory. Transfer can be made in several ways For Example:
- Brust Transfer : In DMA brust transfer a block sequence consisting of a number of memory words is transferred in a continuous brust while the DMA controller is master of the memory buses. This mode of transfer is needed for fast devices such as magnetic disks.
- Cycle Stealing : It allows the DMA controller to transfer one data word at a time, after which it must return control of the buses to the CPU.
DMA control needs the usual circuit of an interface to communicate with CPU and I/O device. In addition, it needs an address register, a word count register and a set address line. The registers in DMA are selected by the COU through the address bus enabling DS (DMA Select) and RS (Register Select) inputs.
Three Register of DMA Controller
- Address Register : It contains and address to specify the desired location in memory. The address register is incremented after each word that is transferred to memory.
- Word Count Register : It specifies the number of words that must be transferred. This register is decremented by one after each word transfer and the value is internally tested for zero.
- Control Register : If specifies the mode of transfer.
The CPU initializes the DMA by sending the following information through the data bus :
- The starting address of the memory block for read or write.
- The word count, i.e. the number of words in the memory block.
- Control to specify the mode of transfer such as read or write.
- A control to start the DMA transfer.
Once the DMA is initialized, the CPU stops communicating with the DMA unless it receives and interrupts signal or if it wants to check how many words have been transferred.