The basic digital memory circuit is known as FLIP FLOP. A flip flop circuit has two outputs, one for the normal value and one for the complement value of the stored bit. It can be obtained by using NAND and NOR gates. Binary information can enter a flip flop in a variety of ways and gives rise to different types of flip flops. We have many types of flip flops but all of these have the following common features :
- The circuit has two stable states i.e. set (1) and reset (0).
- If the circuit is in set (1) state, it continues to remain in this state and similarly if it is in reset (0) state, it continues to remain in this state until the external signal is changed to change the state.
- 1 Basic Flip Flop Circuit
- 1.1 There are Four types of flip flop
- 1.2 S-R Flip Flop
- 1.3 Clocked S-R Flip Flop
- 1.4 J-K Flip Flop
- 1.5 D-Type Flip Flop
- 1.6 T-Type Flip Flop
Basic Flip Flop Circuit
A flip flop can be obtained by using NAND or NOR gates. We shall be systematically developing a flip flop circuit starting from the fundamental circuit.
Since this information is locked or latched in this circuit, therefore, this circuit is also referred to as a latch.
The latch circuit has two states either 1 or 0.
There are Four types of flip flop
- SR Flip Flop
- JK Flip Flop
- T Flip Flop
- D Flip Flop
S-R Flip Flop
The most fundamental latch is the simple SR latch or SR flip flop, where S and R stand for set and reset. It can be constructed with the help of latch and two more NAND gates.
Truth Table of SR Flip Flop
Clocked S-R Flip Flop
It is often required to set or reset the memory cell in synchronism with a train of pulses known as clock (abbreviated as CK). If a clock input is added to a S-R flip flop, then a clocked S-R flip flop is obtained.
Truth table of clocked S-R flip flop
J-K Flip Flop
JK flip-flop is the modified version of SR flip-flop. It operates with only positive clock transitions or negative clock transitions. JK flip-flop eliminates some limitation of S-R flip flop.
D-Type Flip Flop
The D flip flop can be constructed using either S-R flip flop or J-K flip flop. It has only one input referred to as D-input or data input. Here an invertor is attached between two inputs of flip flop i.e. both the inputs of flip flop can not be same.
Block Diagram of D Flip Flop
When CK=1 and D=0, then J=0 and K=1
By using truth table of JK flio flop, output is 0
When Ck=1 and D=1, then J=1 and K=0. By using truth table of JK flip flop, output is 1
Truth Table of D flip flop
T-Type Flip Flop
T flip – flop is also known as “Toggle Flip – flop”. To avoid the occurrence of intermediate state in SR flip – flop, we should provide only one input to the flip – flop called Trigger input or Toggle input (T). Then the flip – flop acts as a Toggle switch. Toggling means ‘Changing the next state output to complement of the present state output’.